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An investigation was made into the occurrence of substrate surface defects, such as surface pits, low-density regions and burrs, and their effect on fine-line thin-film conductor patterns fabricated on the substrate. Substrate surface quality was characterized through examination of fine-line thin-film test patterns (50-µm lines on 100-µm centers). The results of these observations are summarized in terms of N-, the substrate surface defect density, and f, the frequency of resultant conductor-line imperfections greater in width than some critical size δ. The parameter f is directly related to the expected yield Y for a thin-film interconnect circuit with fine-line conductor length L. A quantitative model is developed which accurately relates N and f to N-(x), the size distribution of surface voids; δ, the critical extent of defect overlap on a conductor line; and D, the width of the conductor line. Application of the model to prediction of the dependence of f and Y on various parameters led to the conclusion that it is important to establish objective criteria as to what constitutes a conductor-line imperfection. A change in definition from the extent to which a conductor line appeared to be open to the overlap of a substrate defect on a conductor line resulted in a tenfold increase in f. This change would result in a fourfold decrease in Y for the case of an interconnect pattern with 500 cm of 50-µm lines. A change in δ from D/3 to 2D/3 resulted in a sixfold decrease in f and a corresponding increase in yield from 20 to 80 percent for the same interconnect circuit.