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A sublithographic antifuse structure for field-programmable gate array applications

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7 Author(s)
Chen, K.-L. ; Texas Instrum. Inc., Dallas, TX, USA ; Liu, D.K.Y. ; Misium, George ; Gosney, W.M.
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The authors demonstrate an antifuse structure with a cell area of 0.2*0.2 mu m/sup 2/ which is fabricated by using the vertical sidewall of a polysilicon interconnect layer and two-mask patterning and etching steps. The antifuse is constructed in such a way that its vertical dimension is determined by the thickness of the polysilicon layer, and its horizontal dimension is determined by two-mask patterning and etching steps. For a conventional contact-hole type of structure, a 0.2- mu m lithographic capability would be required to achieve the same antifuse cell size. It is also demonstrated that the time-dependent dielectric breakdown (TDDB) reliability of this sidewall antifuse is as good as that of a conventional planar contact-hole antifuse.<>

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Electron Device Letters, IEEE  (Volume:13 ,  Issue: 1 )