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Design and performance of 0.1- mu m CMOS devices using low-impurity-channel transistors (LICT's)

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12 Author(s)
M. Aoki ; Hitachi Ltd., Tokyo, Japan ; T. Ishii ; T. Yoshimura ; Y. Kiyota
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0.1- mu m CMOS devices using low-impurity-channel transistors (LICTs) with dual-polysilicon gates have been fabricated by nondoped epitaxial growth technology, high-pressure oxidation of field oxide, and electron-beam lithography. These devices, with gate lengths of 0.135 mu m, achieved normal transistor operation at both 300 and 77 K using 1.5-V supply voltage. Maximum transconductances are 203 mS/mm for nMOS transistors and 124 mS/mm for pMOS transistors at 300 K. Low-impurity channels grown on highly doped wells provide low threshold voltages of about 0.35 V for nMOS transistors and about -0.15 V for pMOS transistors at 77 K, and preserve good turn-offs with subthreshold swings of 25 mV/decade at 77 K. LICTs suppress short-channel effects more effectively, compared with conventional devices with nearly uniform dopings.<>

Published in:

IEEE Electron Device Letters  (Volume:13 ,  Issue: 1 )