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A time-based model for investigating parallel logic-level simulation

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1 Author(s)
Bailey, M.L. ; Dept. of Comput. Sci., Arizona Univ., Tucson, AZ, USA

A model for studying the effects of timing models and synchronization strategies for event-driven parallel logic-level simulation is presented. Two timing models, variable-delay and unit-delay, and two synchronization strategies, synchronous and conservative asynchronous, are discussed. The average parallelism of circuits using the two timing models are compared, and the execution times of circuits using various timing models and synchronization strategies are considered. It is shown that the circuit parallelism using unit-delay timing provides an upper bound on that of any timebase used in variable-delay timing and that with either timing model, the execution time of the conservative asynchronous strategy is a lower bound over the synchronous strategy, assuming an unlimited number of processors. However, assuming that all events take the same amount of time, it is shown that with unit-delay timing, the execution time of the synchronous strategy equals that of the asynchronous strategy

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:11 ,  Issue: 7 )

Date of Publication:

Jul 1992

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