By Topic

A high-speed FFT unit based on a low cost digital signal processor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
P. Tortoli ; Dept. of Electron. Eng., Florence Univ., Italy ; F. Andreuccetti

The implementation of a high-speed 128-complex-point FFT (fast Fourier transform) system is described. It is based on a low-cost programmable NMOS digital signal processor (DSP) with a limited amount of memory. For this reason, its use has been restricted so far, to short transforms (Nor=128), performed at a lower speed. This inherent compromise has been overcome by subsequently calculating eight length-16 and sixteen length-8 FFTs, so that a limited data memory is occupied at each processing step. Moreover, the iteration of basics short transform subroutines allows sizable reduction of the requested program memory without sacrificing the processing speed. As a result, by using a single DSP in a simple architecture, 128 complex points are analyzed at a throughput rate of several tens of kilohertz. The possible application of the approach to larger FFTs, as well as to other transforms, is discussed. A brief description is also given of how a higher operating speed could be obtained by pipelining the FFT unit without having recourse to expensive devices.<>

Published in:

IEEE Transactions on Circuits and Systems  (Volume:35 ,  Issue: 11 )