By Topic

Top-down design process for gate-level combinational logic design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Sandige, R.S. ; Dept. of Electr. Eng., Wyoming Univ., Laramie, WY, USA

A pedagogical process for designing gate-level combinational logic circuits is described. The process can be used for either combinational logic circuits or the combinational logic sections of sequential logic circuits. Positive logic signals (active high signals) as well as negative logic signals (active low signals) can be used in the design process. The top-down design process allows the student to draw functional logic diagrams in a rather routine manner using the positive logic convention, or the direct polarity convention. After obtaining functional logic diagrams, realizable logic diagrams can be easily obtained using any of the common off-the-shelf gate types including AND, OR, NAND, and NOR elements with appropriate inverter symbols. The advantage of the top-down design process is that students can very easily understand and implement gate-level combinational logic functions. Examples are provided to illustrate the top-down design process in teaching combinational logic design

Published in:

Education, IEEE Transactions on  (Volume:35 ,  Issue: 3 )