By Topic

Cache memories for data flow machines

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Takesue, M. ; NTT Software Lab., Tokyo, Japan

Cache memories for dataflow machines are presented, and, in particular, four design principles for reducing the working set size of dataflow caches are introduced. They are (1) controlling the number of active state processes, (2) optimizing instruction addresses, (3) using a block-structured operand matching/waiting memory, and (4) making deterministic replacements. Based on these principles, instruction and operand caches are organized. A bypass control is also devised that enables cache block replacement to overlap with normal cache access. Miss ratio and performance of the caches are evaluated on a register transfer level simulator of a dataflow machine. The results show that the instruction cache of 1 k words and the operand cache of 2 k words achieve sufficiently low miss ratios. The bypass control compensates for the bandwidth of a narrow swapping channel to the extent that about eight dataflow processors with the caches can be integrated in an LSI chip

Published in:

Computers, IEEE Transactions on  (Volume:41 ,  Issue: 6 )