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1 Author(s)
Gaertner, W.W. ; CBS Laboratories, Stamford, Conn.

It is shown, with the aid of several examples, that as microelectronic circuits with a power consumption of a few microwatts have been engineered for practical systems applications, it becomes technologically feasible to build silicon transistors with substantial power gain at a supply power of one nanowatt or lower. The investigation covers the limitations with respect to gain, speed, size, and noise which one encounters as the supply power for circuits is reduced below the microwatt level, and also the experimental results that have already been achieved in the laboratory. The design characteristics of nanowatt transistors, plus guidelines for their practical fabrication, are derived. Figures of merit for minimum-power devices and circuits are defined. The performance of experimental transistors and of analog and logic circuits operating at 20 nanowatts and lower is described. The four-pole parameters and the maximum achievable power gain of a transistor operating in the nanoampere range are derived, and the necessary source and load resistors are shown to rise into the 100-megohm range and higher, so that they may become a limitation to further power reduction before the transistor itself loses its capacity for power gain. The speed of small-signal and large-signal nanowatt circuits is investigated and found to be limited only by RC time constants. With the required high resistors, the device capacitances and, more important, the circuit stray capacitances must be reduced by several orders of magnitude, with 10-15farads as a technological goal. This means not only that the conducting cross section of all devices and interconnections must be reduced approximately proportional to the bias currents but that the length of resistors and intercounections and thus the distance between adjacent circuits must be reduced by approximately the same ratio. It is shown that circuit geometries will have to undergo major changes, that nanowatt microelectronic circuits most likely will not be based on silicon as the host crystal, and that entire systems rather than individual devices and circuits will have to be fabricated in the same crystal or on the same substrate. Assuming certain size restrictions derived earlier by Wallmark and Marcus [45], it appears at p- resent that nanowatt circuits will be restricted to operating frequencies below one megacycle. Transistors with a collector area of 3 by 3 microns, and resistors with a linewidth of less than one micron, a length of less than 100 microns, and sheet resistances as high as 100 megohms per square are established as technological goals. These goals do not violate any laws of device physics, but the technology necessary to achieve them is not known at present in all cases. Electron and ion beams are noted as potentially important tools in the advanced technology necessary to reach such extremely small size in integrated structures. Noise is shown not to be a basic limitation. Billion-element systems with a power consumption of a few watts are found to be technologically--though not yet economically-feasible, and the conclusion is drawn that solid-state technology will allow the building of electronic systems that simulate the function of major biological nerve systems in the same volume and with the same power consumption as their living counterparts.

Published in:

Proceedings of the IEEE  (Volume:53 ,  Issue: 6 )