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Detection of bridging faults in programmable logic arrays

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3 Author(s)
Saluja, K.K. ; Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA ; Liu, C.-Y. ; Reddy, S.M.

A test set and a testable design for MOS PLAs are proposed. The new design, which modifies a PLA by adding one extra line in the AND plane and one extra line in the OR plane, can detect bridging faults. Furthermore, the design modification requires very low area overhead and is independent of the personality of the PLA under test.

Published in:

Electronics Letters  (Volume:28 ,  Issue: 13 )