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Modeling and testing of SRAM for new failure mechanisms due to process variations in nanoscale CMOS

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4 Author(s)
Qikai Chen ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Mahmoodi, H. ; Bhunia, S. ; Roy, K.

In this paper, we have made a complete analysis of the emerging SRAM failure mechanisms due to process variations and mapped them to fault models. We have proposed two efficient test solutions for the process variation related failures in SRAM: (a) modification of March sequence, and (b) a low-overhead DFT circuit to complement the March test for an overall test time reduction of 29%, compared to the existing test technique with similar fault coverage.

Published in:

VLSI Test Symposium, 2005. Proceedings. 23rd IEEE

Date of Conference:

1-5 May 2005