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Survey of design and process failure modes for high-speed SerDes in nanometer CMOS

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1 Author(s)
Dryden, C. ; Metrologic Instruments, Blackwood, NJ, USA

This paper gives an overview of reported design-and process-related electrical performance failure modes for high-speed (> 1 GHz) serial interfaces fabricated using CMOS processes ≤130 nm. Effects of various defects on observable performance at the I/O pins are summarized, along with ATE test technology implications.

Published in:

VLSI Test Symposium, 2005. Proceedings. 23rd IEEE

Date of Conference:

1-5 May 2005