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Measures to improve delay fault testing on low-cost testers - a case study

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5 Author(s)
M. Beck ; Infineon Technol. AG, Munich, Germany ; O. Barondeau ; F. Poehl ; Xijiang Lin
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This paper addresses delay test for SOC devices on low-cost testers. The case study focuses on the at-speed testing for a state-of the-art microcontroller device by using an on-chip high-speed clock generator. The experimental results show that the simple on-chip high-speed clock generator is not sufficient to reach both high fault coverage and acceptable pattern count. Meanwhile, at-speed test constraints, required to enable the delay test on low cost testers, have a significant impact on test generation results. DFT techniques to increase fault coverage and to reduce pattern count are discussed.

Published in:

23rd IEEE VLSI Test Symposium (VTS'05)

Date of Conference:

1-5 May 2005