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Static frequency dividers with a maximum clock frequency > 110 GHz were designed and fabricated in a narrow mesa InP/In0.53Ga0.47As/InP DHBT technology. Divider operation is fully static, operating from fclk = 4 GHz to 118.70 GHz and dissipating 686.4 mW of power from a -4.2 Volt supply. The circuit employs single-buffered emitter coupled logic (ECL) and inductive peaking. The transistors have an emitter junction width of 0.5 μm and a collector-to-emitter area ratio of 3.0. A microstrip wiring environment is employed for high interconnect density, and to minimize loss and impedance mismatch at frequencies > 100 GHz.