Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

Packaging of multi-core microprocessors: tradeoffs and potential solutions

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Muthana, P. ; Sch. of Electr. & Comput. Eng. Packaging Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA ; Swaminathan, M. ; Tummala, R. ; Sundaram, V.
more authors

Power consumption and interconnect latency are becoming major bottlenecks in the design of high performance computers and microprocessors. In this paper we propose to use a multicore processor approach to improve the performance of a processor. This paper discusses an analysis of the performance trade offs between single and multicore processors based on power, frequency, bandwidth and the role of embedded passives with high density wiring in future packages to support such processors.

Published in:

Electronic Components and Technology Conference, 2005. Proceedings. 55th

Date of Conference:

31 May-3 June 2005