By Topic

Thermal performance of a thin high interconnect density organic substrate for flip-chip applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
V. V. Calmidi ; Endicott Interconnect Technol., Inc., NY, USA

The thermal performance of a thin (0.5 mm), high interconnect density substrate for flip-chip applications (FC-PBGA) has been studied under natural and forced convection conditions per JEDEC standard conditions [1999]. Since the effect of a heat sink not considered, heat conduction within the package and substrate is relatively more important to thermal performance. A package size of 42.5 mm is assumed. The effect of die size, core vias in the substrate, and lid assembly conditions is studied. The lid assembly conditions have the greatest effect on theta-ja (up to 38%). The effect on theta-ja of increasing the number of core vias under the die site is also dependent on the lid assembly. When the lid is attached to a stiffener on the substrate, a negligible change (3%) in theta-ja is observed when the number of core vias is increased (i.e. increasing kzz from 0.6 to 3.1 W/m-K). When a floating lid that is not physically coupled to the substrate is used, up to 9% difference is observed. These and other results are discussed in the light of various conduction heat flow paths within the package.

Published in:

Proceedings Electronic Components and Technology, 2005. ECTC '05.

Date of Conference:

31 May-3 June 2005