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The evaluation of wafer thinning and singulating processes to enhance chip strength

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5 Author(s)
Shoulung Chen ; Electron. Res. & Service Organ. (ERSO), Ind. Technol. Res. Inst. (ITRI), Taiwan ; Tzu-Ying Kuo ; Hsu-Tien Hu ; Jyh-Rong Lin
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For several kinds of advanced applications, such as RFID, telecommunication, portable electronics, or wearable electronics, the need of packaged semiconductor chip thick is getting thinner drastically. One representative technology is to embed an active device into an organic substrate by sequential build-up processes, for example, chip-in-polymer by IZM, chip-scale-module by Fujitsu, bumpless build-up layer by Intel, and chip-in-substrate package by ERSO/ITRI. However, reliability of an ultra-thin chip is decayed dramatically as the decay of chip thickness. This negative result of chip strength reduces the reliability of a semiconductor packages. In this paper, we want to get the optimal processes through the studies on wafer thinning and singulating respectively. As the aforementioned description, we did the sequential experiments on thinning and singulating to find out the optimal processing flow. In the wafer thinning study, the average chip strength of plasma dry etching is enhanced 40 to 50 percentages than standard backside grinding. Because DBG is a good solution for ultra-thin wafer processing, the effect on chip strength is also important in the study for the industry. It is enhanced about 10 percentages. On the other hand, the average chip strength of laser cutting is much lower than standard die dicing. Through the comparison of OM pictures of traditional dicing, DBG, and laser cutting, the chipping situations are observed clearly. DBG plus plasma etching does minimize the chipping to provide a more reliable chip. The study on wafer thinning and singulating processes is evaluated successfully in this paper. There are several methods generated and proved to enhance the strength of an ultra-thin chip. According to the results of the research, the novel, innovative, and leading-edge packaging technology can be realized via the more reliable ultra-thin chips.

Published in:

Electronic Components and Technology Conference, 2005. Proceedings. 55th

Date of Conference:

31 May-3 June 2005