Skip to Main Content
This paper briefly presents how silicon integration and advances in packaging technology have enabled higher performance networking products, and is followed by discussions of how a system-level integrated approach is needed to address the challenges of the next generation products. Different methodologies of integrating memory and ASIC using advanced packaging technologies at both package level and board-/system-level are presented. Both connector-based and SMT based system in package (SiP) solutions with either flip-chip bare-die or BGA technologies are evaluated. Impact of each technology on product designs at silicon, substrate, and board level, as well as the effects on product manufacturability and reliability are discussed.
Date of Conference: 31 May-3 June 2005