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3D stacked flip chip packaging with through silicon vias and copper plating or conductive adhesive filling

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4 Author(s)
S. W. R. Lee ; Dept. of Mech. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China ; R. Hon ; S. X. D. Zhang ; C. K. Wong

Three dimensional packaging is emerging as the solution for microelectronics development toward system on chip (SOC) and system in package (SIP). 3D flip chip structures with through silicon vias (TSVs) have very good potential for the implementation of 3D packaging. In this study, a prototype of 3D stacked flip chip packaging with TSVs is designed and fabricated. Fundamental techniques for this prototype fabrication are studied and discussed in detail. The formation of TSVs is by the deep reactive ion etching (DRIE) process and the plugging of TSVs may be done by either copper plating or conductive adhesive dispensing. In addition to the conceptual design, all wafer level processes are described and the subsequent die stacking assembly is also presented in this paper.

Published in:

Proceedings Electronic Components and Technology, 2005. ECTC '05.

Date of Conference:

31 May-3 June 2005