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A new defect in which a flip chip device "floats" over the board surface after chip placement is appearing in processing flip chip components using no-flow underfills. This defect has the potential to significantly lower process yield when process variables are not properly controlled. In fact, it was found that much of the yield loss observed post reflow is attributable to "chip floating." An experimental investigation of the floating phenomena has been conducted to understand the underlying physics of the floating phenomena and identify critical process variables so that this process defect can be eliminated. A supporting process model has been developed that will allow the process to be designed eliminating the defects. The critical process variables include chip placement speed, chip placement force, dwell time, deposited underfill mass and underfill material properties such as viscosity, density, surface tension, wetting speed on the board, etc. A test chip and board was specially designed so that chip floating over the board can be easily detected. To validate the model, the effects of the critical process variables on chip floating were investigated by a series of experiments, and the results were compared to the model's predictions. Chip floating occurs due to high pressure formed in the underfill fillet just after its being squeezed by the compression placement. It has been observed in the real flip chip placement process that the chip floats in almost all cases in which no dwell time is provided. This suggests that a minimum of dwell time should be designed into the placement process against chip floating defects. Real time observation of the flip chip devices during placement provide a key source of data to expose the underlying physics of the process defect.