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An integrated folded-patch chip-size antenna using high-resistivity polycrystalline silicon substrate

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5 Author(s)
Mendes, P.M. ; Dept. of Industrial Electronics, University of Minho, Portugal ; Polyakov, A. ; Bartek, M. ; Burghartz, J.N.
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High-resistivity polycrystalline silicon (HRPS) wafers are utilized as low-loss substrates for three-dimensional integration of on-chip antennas in wafer-level chip-scale packages (WLCSP), Sandwiching of HRPS and silicon wafers enables to integrate complex RF passives with a spacing of ≫ 150 μm to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form factor and avoiding any additional RF loss. A folded-patch antenna with dimensions of 2.5x2.5x1 mm3, operating at 5.7 GHz was analysed considering a 10 kΩ-cm HRPS wafer. The antenna has a -10 dB return loss bandwidth of 50 MHz and an efficiency of 58 %, a performance comparable to glass substrates.

Published in:

Advanced Semiconductor Devices and Microsystems, 2004. ASDAM 2004. The Fifth International Conference on

Date of Conference:

17-21 Oct. 2004