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In this paper, V-band high-order frequency divider monolithic microwave integrated circuits (MMICs) showing wide bandwidth and low-power dissipation are presented. For high-order (divide-by-four) frequency division, a super-harmonic signal is injected into a self-oscillating subharmonic mixer loop consisting of cascode field-effect transistors (FETs). Cascode FET-based harmonic injection locking allows high-frequency operation, simple circuit configuration, reduced FET count, and thus, low dc power consumption. Bias circuits and quarter-wavelength stubs are used to effectively suppress unwanted harmonic and spurious signals in the oscillation loop. A simple analysis method employing two-tone harmonic-balance simulation and an ideal directional coupler is developed to optimize the performance of the high-order divider. The designed V-band frequency dividers are fabricated with a commercial 0.15-μm GaAs pseudomorphic high electron-mobility transistor foundry. The measurement of a divide-by-four MMIC shows a bandwidth of 2.81 GHz around 64.0 GHz under very small dc power consumption of 7.5 mW. The circuit concept has been extended to a divide-by-five MMIC by adding a frequency doubler in the feedback loop, which shows the bandwidth of 1.02 GHz at V-band. To the best of our knowledge, the frequency dividers of this study show the best performance in terms of division order and dc power consumption among the reported millimeter-wave analog frequency dividers at V-band and above.