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Proving finite state machines correct with an automaton-based method

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4 Author(s)
Camurati, P. ; Dipartimento di Automatica e Inf., Politecnico di Torino, Italy ; Gilli, M. ; Prinetto, P. ; Reorda, M.S.

The authors present a method to prove equivalence of a pair of FSMs, described at the gate level with D-type flip-flops and a reset signal available to bring them into the all-zero initial state. This method restricts investigation to that minimum subset of states that can be reached from the reset condition and are necessary to reach the goal. The equivalence condition is expressed in theoretical terms within the framework of the product machine. Without any loss of information, it is possible to reduce the product machine to a deterministic finite automaton (DFA). considerably reducing the number of states. The DFA is dynamically built by an explicit enumeration algorithm and, in general, only a very small part of the automaton is actually considered. The equivalence condition becomes a proof of the reachability of the DFA's final state. Search is performed in breadth-first. Experimental results on some pairs of ISCAS'89 circuits are reported

Published in:

VLSI, 1991. Proceedings., First Great Lakes Symposium on

Date of Conference:

1-2 Mar 1991

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