Error rate test of large-scale SFQ digital circuit systems

We have been developing large-scale SFQ digital circuit systems and have shown the successful demonstration of our prototype SFQ microprocessors and memories. Their circuit scale is now over several thousands of junctions. One question arising in such large SFQ circuits is whether their error rate is low enough for digital applications. In this study, we have examined the error rate of circuit components of our microprocessor. An error rate test system for a program counter (PC) of the CORE1 microprocessor was made using Nb 2.5 kA/cm² process. The system is composed of a clock generator, a comparator and a 16-bit PC under test. It was found from the experiment that the system error rate of the 16-bit PC is lower than 10^-8, which corresponds to a bit-error-rate better than 10^-12. We have also evaluated a timing jitter of the clock generator and an effective temperature of the PC based on the experimental results.