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We have been investigating a design methodology of SFQ logic circuits based on the binary decision diagram (BDD). In the previously proposed BDD SFQ logic circuits, we have used one-to-two binary switches as a node cell in a BDD tree. In this study we will propose a new implementation method of SFQ BDD circuits, in which two nodes are implemented by using a 2-input 2-output switch gate. By employing the new approach, we have designed and implemented a one-bit full adder using the NEC 2.5 kA/cm2 Nb standard process and the CONNECT cell library. The maximum operating frequency of the full adder was found to be 40 GHz by circuit simulations and 32.8 GHz by on-chip high-speed tests.