Design and implementation of stochastic neurosystem using SFQ logic circuits

We propose a stochastic neurosystem using SFQ logic circuits and design the main components with the following functions: carrying out the multiplication of an input to a neuron on a synaptic weight value, integrating pulses to generate a membrane potential, and generating the output of a neuron. We simulate some circuits by JSIM and confirm their correct operation. We compare two methods of multipliers: using a comparator and using a divider. The multiplication using the divider is effective with respect to integration, and reduces the accumulation time N/sub a/ required for higher precision operations. We designed a 4-bit up/down counter assuming the NEC 2.5 kA/cm/sup 2/ Nb/AlO/sub X//Nb standard process. We show that it is possible to compose the activation function circuit using a comparator.