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Delay analysis for superconductive Single Flux Quantum (SFQ) logic is performed for Self-Timing-Aligned Clock Synchronization Technique (STAC). With its pipelined-structure, the SFQ generates and propagates pulses that are to be processed sequentially through serial-connected functional logic blocks, and thus it is critical to acquire a ultra-high-speed and exactly synchronized clock/control signals with a few pico-second resolution. Both passive and Josephson-Junction circuits are investigated for the delay control. These delays, being connected in parallel with input line, and to the clocked-power/control node, produce a self-timing-aligned synchronization. Ways to achieve precision delays are seek by using Mo resistors along with junction inherent capacitors. Both current margins for the bias and critical timing information for the maximum throughput are also investigated. Layouts for the test SFQ circuits, such as D- and RS-flip-flops are done with XIC, and verifications are done through WRSpice with Hypres process parameters.