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Synchronous design is generally used in SFQ digital systems at present. In large-scale SFQ digital systems, however, the introduction of asynchronous design is required due to the large clock skew in the clock distribution network and complexity in the timing design at high clock rate. We have proposed a hierarchical design approach using asynchronous SFQ circuits with handshaking protocol for asynchronous data transfer. In our asynchronous approach, each circuit module is designed based on a data driven self-timed (DDST) architecture. A handshaking protocol is also used to ensure the logical ordering in data communication between the modules, where we have adopted bit-serial architecture to reduce the communication costs in handshaking. One issues in the bit-serial handshaking (BSHS) system is the synchronization of the input data when the module has multiple input ports. In this study, we have designed an SFQ BSHS system with multiple input ports, where Muller C-elements is used to synchronize the multiple input data. We have designed and implemented a BSHS half adder using NEC 2.5 kA/cm2 Nb standard process to demonstrate asynchronous addition of two input data at high speed. We have successfully confirmed its correct operation at about 20 GHz.