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IFFT-FFT core architecture with an identical stage structure for wireless LAN communications

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3 Author(s)
M. Serra ; Univ. de Vic, Barcelona, Spain ; P. Marti ; J. Carrabina

This work shows the design of the IFFT module corresponding to the baseband processing of an OFDM transmitter according to the IEEE802.11a-g and Hiperlan/2 standard. This module will be included in a future OFDM demonstrator, which will be implemented into a programmable logic device. We have used our own algorithm for IFFT computing. It is based on the recursive properties called decimation. This algorithm offers optimal characteristics for the hardware implementation: a high degree of parallelism and exactly the same interconnection pattern between any of the algorithm stages. A new point of view in the prototyping design flow and the verification process comes from the use of the last generation system level design environments for DSPs into FPGAs. These environments, called visual data flows, are ideally suited for modeling DSP systems since they allow a high level of functional abstraction with different data types and operators.

Published in:

Signal Processing Advances in Wireless Communications, 2004 IEEE 5th Workshop on

Date of Conference:

11-14 July 2004