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The design of PCI Express for future communication platform

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2 Author(s)
Eugin Hyun ; Dept. of Electron. Eng., Yengnam Univ., Gyeongsangbuk, South Korea ; Kwang-Su Seong

We design a PCI Express controller for endpoint (APCE). APCE supports the full functionality of the transaction layer and data link layer of PCI Express. We propose an efficient buffer management scheme for APCE to obey the replay mechanism and it can dynamically adjust the size of a replay buffer space. We employ 80C51 to manage the designed functional blocks in APCE effectively, and implement the real-time OS, MicroC/OS II, on 80C51. We also code software under a real time environment. This coded software covers supporting the replay mechanism, checking and generating error messages, processing TLP (transaction layer packet) acknowledgment, and management for exchanging flow control. To verify APCE, we built a test bench including behavioral models of host bridge, local master, and local slave. We also propose an effective verification for compliance and corner case testing when using a behavioral reference model of APCE, random generator, and compare engine.

Published in:

Intelligent Signal Processing and Communication Systems, 2004. ISPACS 2004. Proceedings of 2004 International Symposium on

Date of Conference:

18-19 Nov. 2004