By Topic

Acquisition performance of a digital phase locked loop with a four-quadrant arctan phase detector

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Kandeepan, S. ; Wireless Signal Process. Group, Nat. ICT Australia, Braddon, ACT, Australia ; Reisenfeld, S.

The acquisition performance of a digital phase locked loop (DPLL) with a four-quadrant arctan based phase detector (PD) is discussed. In the noiseless case, unlike the traditional sine function based phase locked loops, the acquisition process of the four-quadrant arctan based phase locked loops is less tedious. We look into the pull-in process together with a time-series analysis of the DPLL for the noiseless case. The phase-plane portrait of the loop is also discussed, for both the noiseless and the noisy conditions.

Published in:

Intelligent Signal Processing and Communication Systems, 2004. ISPACS 2004. Proceedings of 2004 International Symposium on

Date of Conference:

18-19 Nov. 2004