By Topic

Principles of sequential-equivalence verification

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
2 Author(s)
Mneimneh, M.N. ; Dept. of Comput. Sci. & Eng., Michigan Univ., Ann Arbor, MI, USA ; Sakallah, K.A.

Traditionally, designers use simulation to check the functional equivalence of specification and implementation models. Although simulation can eliminate some or most design errors, it can never completely certify design correctness. Formal equivalence verification (FEV) is a viable alternative that has gained wide industrial acceptance. FEV, which uses automata theory and mathematical logic to formally reason about the correctness of design transformations, is broadly divided into two categories: combinational and sequential. This article is a general survey of conceptual and algorithmic approaches to sequential equivalence checking. Although this fundamental problem is very complex, recent advances in satisfiability solvers and ATPG approaches are making good headway.

Published in:

Design & Test of Computers, IEEE  (Volume:22 ,  Issue: 3 )