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New test paradigms for yield and manufacturability

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1 Author(s)
Madge, R. ; LSI Logic, Milpitas, CA, USA

As CMOS technology continues its trend down the technology nodes through 90 nm to 14 nm, our industry faces the challenge of achieving necessary yield as we integrate more on-chip circuitry having more complex, advanced process technologies. These technologies are generally less scalable than in the past, which means we're involved in a completely new yield ramp almost every two years. Closing the loop from semiconductor manufacturing back to design and process development is crucial. The author explored the nanometer-era semiconductor yield challenges, classified the yield limiting problems, and discussed how to close the loop back to design and process development. This analysis, summarized in this perspectives, reveals the key role of test and the data it generates to optimize semiconductor yield for the next generation.

Published in:

Design & Test of Computers, IEEE  (Volume:22 ,  Issue: 3 )