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Test scheduling for core-based SOCs

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4 Author(s)
Zhang Yong guang ; Inst. of Inf. & Commun. Eng., Zhejiang Univ., Hangzhou, China ; Xu Yuan xin ; Dong Bin ; Wang Kuang

In this paper, the modeling of system-on-a-chip (SOC) test optimization has been formulated with different precedence, resource and core constraints. A neural network combined with heuristic algorithm has been developed to solve the large size SOC test problems. As demonstrated by the results that computer implement the developed method can not only solve the large size SOC test problems, but is also capable of finding the optimal solutions within reasonable computing time.

Published in:

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on  (Volume:2 )

Date of Conference:

18-21 Oct. 2004

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