By Topic

Efficient 3-D interconnect capacitance extraction based on direct solving techniques for system with multiple right-hand sides

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Hong Liu ; Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China ; Wenjian Yu ; Zeyi Wang

Under the current deep submicron technology, the capacitance extraction of interconnects has become more and more important and more coupling capacitances need to be extracted accurately rather than those related with a single master net for high-precision time verification. Therefore, for a simulated structure, IV voltage must be set on different conductors one by one and the corresponding linear system with multiple right-hand sides (RHS) should be solved efficiently. In this paper, direct equation solving techniques are presented to extract the parasitic capacitances with multiple master conductors. Combined with the quasi-multiple medium (QMM) technology, our method exploits the sparsity of the resulted coefficient matrix and is very suitable for the problem with multiple RHS. The experiments on actual interconnect structures have shown that our method is several times faster than the conventional GMRES solver, while preserving the computational accuracy.

Published in:

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on  (Volume:2 )

Date of Conference:

18-21 Oct. 2004