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In this paper, the DC characteristics of MOSFETs are investigated by means of an analytical approach with considerations of the source/drain parasitic resistance. Experimental data of MOS devices for DRAM design and results of TCAD simulation are used to verify the accuracy of theoretical calculation. It is found that both the source and drain resistances can induce a large reduction in the drain current in the linear region, but only the source resistance can cause a large reduction in the drain current in the saturation region. Moreover, the drain current deduction due to the source/drain resistance increases with decreasing channel length and oxide thickness.