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A low-power SRAM using hierarchical bit line and local sense amplifiers

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2 Author(s)
Byung-Do Yang ; Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea ; Lee-Sup Kim

This paper proposes a low power SRAM using hierarchical bit line and local sense amplifiers (HBLSA-SRAM). It reduces both capacitance and write swing voltage of bit lines by using the hierarchical bit line composed of a bit line and sub-bit lines with local sense amplifiers. The HBLSA-SRAM reduces the write power consumption in bit lines without noise margin degradation by applying a low swing signal to the high capacitive bit line and by applying a full swing signal to the low capacitive sub-bit line. The HBLSA-SRAM reduces the swing voltage of bit lines to VDD/10 for both read and write. It saves 34% of the write power compared to the conventional SRAM. An SRAM chip with 8 K×32 bits is fabricated in a 0.25-μm CMOS process. It consumes 26 mW read power and 28 mW write power at 200 MHz with 2.5 V.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:40 ,  Issue: 6 )