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Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture

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4 Author(s)
R. Nonis ; Univ. of Udine, Italy ; N. Da Dalt ; P. Palestri ; L. Selmi

This paper describes the modeling, design, and characterization of a low-jitter 2.4-GHz LC-VCO PLL architecture realized in a standard 0.12-μm CMOS technology. It features an analog dual control loop for fine and coarse VCO tuning that allows very low VCO gain (60 MHz/V) for noise rejection while maintaining a wide tuning range. The coarse input of the VCO is driven by an analog circuit that adjusts the VCO gain in a continuous manner. Measurements demonstrate an integrated jitter of 0.74 ps that is 43% lower compared to results from a standard PLL topology (STD PLL) with a single control loop. The PLLs have the same bandwidth and output frequency range and were built on the same wafer for comparison. The circuit area of the proposed LC-VCO PLL is 0.7 mm2 and the power consumption is 32 mW. The area and power consumption of the proposed LC-VCO PLL are less than 1% larger compared to the STD PLL.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:40 ,  Issue: 6 )