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An adaptive cache coherence scheme for hierarchical shared-memory multiprocessors

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3 Author(s)
Quing Yang ; Dept of Electr. Eng., Rhode Island Univ., Kingston, RI, USA ; Thangadurai, G. ; Bhuyan, L.N.

The paper considers a large scale, cache-based multiprocessor that is interconnected by a hierarchical network such as hierarchical buses or a multistage interconnection network (MIN). An adaptive cache coherence scheme for the system is proposed based on a hardware approach that handles multiple shared reads efficiently while reducing the network traffic. The new protocol allows multiple copies of a shared data block in the hierarchical network, but minimizes the cache coherence overhead by dynamically partitioning the network into sharing and non-sharing regions based on program behaviors. The new cache coherence scheme effectively utilizes the bandwidth of the hierarchical networks and exploits the locality properties of parallel algorithms. The simulation results show that the new protocol gives 15% to 30% performance improvement over some existing cache coherence schemes for the similar systems over a wide range of workload parameters

Published in:

Parallel and Distributed Processing, 1990. Proceedings of the Second IEEE Symposium on

Date of Conference:

9-13 Dec 1990