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A parallel distributed processing approach to VLSI global routing

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2 Author(s)
Provence, J. ; Dept. of Electr. Eng., Southern Methodist Univ., Dallas, TX, USA ; Naganathan, S.

Two major issues which must be addressed in the VLSI layout methodology are placement and routing. Traditionally, these two issues are handled separately to reduce the computational complexity. But these two issues are interrelated as routability must be guaranteed for placement in addition to the geometrical constraints. The authors propose a distributed processing approach for solving this integrated routing-placement problem. The distributed processing network is roughly based on the Hopfield model and is designed to minimize an objective function similar to that used for the traveling salesman problem. Minimization of the objective function provides cell placements such that the total net span is minimized. The idea is based on the notion of slicing the slice sequencing in a hierarchical fashion

Published in:

Parallel and Distributed Processing, 1990. Proceedings of the Second IEEE Symposium on

Date of Conference:

9-13 Dec 1990