Optimization of device structure of SiCOI MESFET with dielectric groove isolation

The optimization of groove width and groove depth of a SiCOI MESFET with dielectric groove isolation is studied. Simulation results show that when the groove width is 2 /spl mu/m and groove depth is 0.15 /spl mu/m, the breakdown voltage is greatly increased and a large decrease of the drain characteristics does not occur, and the device gains the largest output power which is equal to 13 W/mm.