By Topic

Multiple instruction streams in a highly pipelined processor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Sato, M. ; Res. Dev. Corp. of Japan, Tokyo, Japan ; Ichikawa, S. ; Goto, E.

In a highly pipelined processor, instruction dependencies involving both and control information often limit its potential performance. A cyclic pipeline machine allows multiple instruction streams to share these pipeline stages in time to remove the data and control dependencies. These multiple instruction streams exploit more parallelism in parallel programs. It provides an alternative architectural solution for new technologies such as GaAs and Josephson logic device, which prefer a highly pipelined architecture. The authors define the basic model of a cyclic pipeline machine, and examine the performance improvement of various configurations of cyclic pipeline machines compared to the same degree of pipelining of a conventional pipelined processor. The simulation results indicate that pipelining in the individual instruction streams increases the performance to maximize the utilization of resources in a highly pipelined processor

Published in:

Parallel and Distributed Processing, 1990. Proceedings of the Second IEEE Symposium on

Date of Conference:

9-13 Dec 1990