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An efficient framework for accelerating functional verification of microprocessor

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3 Author(s)
Wang Zuo-dong ; Inst. of Microelectron., Tsinghua Univ., Beijing, China ; Su Ya-juan ; Wei Shao-jun

The paper presents a simulation-based function verification framework featured by two efficient acceleration techniques, namely "self-verifying" and "co-simulation of mixed models". The former automates the verification process over the whole vector space by eliminating manual interference, the effect of which is directly proportional to the size of the vector space and the average vector size. The latter reduces the time required to simulate a full-chip netlist from exponential to linear relationships with the number of modules by co-simulating the mixed models of RTL and netlist. The benefit of this framework was well exhibited in the verification practice of a 32-bit high-end processor. A prototype processor fabricated on a 0.18 μm CMOS process technology functioned properly under a system environment test, which indicated that the verification framework presented is feasible.

Published in:

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on  (Volume:3 )

Date of Conference:

18-21 Oct. 2004