FPGA implementation of digital IF processing in HFGWR

Software radio has become the focus of research in communication. Radar based on software radio technology overcomes the simplicity and inflexibility of conventional radar. Digital IF, one of its key technologies, is a typical application of multirate signal processing theory. The paper studies the high decimation ratio of the digital downconverter in HF ground wave radar (HFGWR), and especially analyzes a multistage decimation algorithm based on a CIC (cascaded integrator-comb) filter and an HB (half-band) filter. By comparison, the optimal design can save 92.6% of the logic resources over that of a single stage polyphase design, and can be well implemented in a single FPGA chip (such as XC2S200) for four receiver channels. Furthermore, the filtering performance is better than design requirements.