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A complete BIST scheme for ADC linearity testing

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4 Author(s)
Wu Guanglin ; Nat. ASIC Syst. Eng. Center, Southeast Univ., Nanjing, China ; Ling Ming ; Rao Jin ; Shi Longxing

In this paper, we presented algorithms for testing gain error, offset error, differential nonlinearity (DNL) and integral nonlinearity (INL) of analog-to-digital converters (ADC), and proposed an easily integrated built-in self-test (BIST) scheme on chip, which has been designed using Chartered 0.35 μm technology. The experimental results show that the proposed BIST scheme has low area overhead, low test cost and high test accuracy.

Published in:

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on  (Volume:3 )

Date of Conference:

18-21 Oct. 2004

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