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System level asynchronous virtual pipeline on dynamically and partially reconfigurable architecture

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5 Author(s)
Min Li ; Inst. of VLSI Design, Zhejiang Univ., Hangzhou, China ; Xiaobo Wu ; Menglian Zhao ; Hui Wang
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Nowadays, dynamically and partially reconfigurable architectures (DPRA) have been widely adopted by backbone equipment manufacturers to tackle the market pressure in terms of cost, performance, time to market, etc. Among all the advantages of DPRA, the run time rapid reconfiguration is still not fully utilized to deliver the greatest potential. In our work, a system level asynchronous virtual pipeline (SLAVP) is studied on a block partitioned DPRA for throughput critical telecommunication applications. Unlike previous approaches, SLAVP does not constrain the computation of pipeline stages to be strictly balanced, and it does not constrain the input specification to be a sequential data flow graph. By swapping tasks in/out, more logic stages are implemented than the physically available resources, and this achieves greater efficiency on the DPRA. In addition, we proposed a method to transform the problem to a generic system level synthesis problem, and then developed a hierarchical genetic algorithm (GA) based tool for synthesis on a block partitioned DPRA.

Published in:

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on  (Volume:3 )

Date of Conference:

18-21 Oct. 2004