By Topic

Research on the routing algorithm of SRAM-based FPGA

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Gu Haiyun, ; Dept. of Electron., Southeast Univ., Nanjing, China ; Xu juyan

SRAM-based FPGA, as the hardware basis of reconfigurable computing will be a significant part of reconfigurable SoC, the next generation IC product. An effective routing algorithm for FPGA is necessary for developing a design tool for R-SoC. This paper suggests a taxonomy for presenting FPGA routing algorithms, introduces and analyzes the typical algorithms of each kind, and for the most importance, concludes a generalized model for FPGA routing, including a generalized routing flow, parameters, and cost function. Particular routing algorithms can be derived from this model.

Published in:

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on  (Volume:3 )

Date of Conference:

18-21 Oct. 2004