By Topic

Input collapse of CMOS logic gates with a series-connected MOSFET chain

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Xueping Jiang ; Lattice Semicond. Corp, San Jose, CA, USA ; Jayasumana, A.P.

We propose a generic series-connected MOSFET chain model (SMCM) extending the PDSMM, to describe the peculiar DC characteristics of a series MOSFET chain. Initial state propagation delays (ISPD) are defined as propagation delays due to initial states of intermediate nodes of a series-connected MOSFET chain. Two extreme and important ISPD, called as fast ISPD and slow ISPD, are introduced. The effect of input patterns of CMOS logic gates on propagation delays in the two ISPD is discussed. Finally, an efficient mapping algorithm for every possible input pattern to an equal input ramp is introduced.

Published in:

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on  (Volume:3 )

Date of Conference:

18-21 Oct. 2004