A fast VLSI architecture for two-dimensional discrete wavelet transform based on lifting scheme [image compression applications]

This paper proposes a novel fast architecture for a 2D discrete wavelet transform by using a lifting scheme, Parallel and embedded decimation techniques are employed to optimize the architecture, which is mainly composed of two horizontal filter modules and one vertical filter module, working in parallel and pipeline fashion with 100% hardware utilization. The architecture is designed to generate two outputs in one working clock cycle, with every two subbands coefficients alternately. The total time for computing J levels of decomposition for an N/spl times/N image is approximately 2N/sup 2/(1-4/sup -J/)/3 clock cycles. In comparison with the other devices reported in previous literature, the design has many advantages including lower hardware complexity and area and power efficiency. The design is also fast, regular and simple, as well as well suited for VLSI implementation.