By Topic

A fast VLSI architecture for two-dimensional discrete wavelet transform based on lifting scheme [image compression applications]

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Chengyi Xiong ; Key Lab. of Educ. Minist. for Image Process. & Intelligent Control, Huazhong Univ. of Sci. & Technol., Wuhan, China ; Jinwen Tian ; Liu, Jian

This paper proposes a novel fast architecture for a 2D discrete wavelet transform by using a lifting scheme, Parallel and embedded decimation techniques are employed to optimize the architecture, which is mainly composed of two horizontal filter modules and one vertical filter module, working in parallel and pipeline fashion with 100% hardware utilization. The architecture is designed to generate two outputs in one working clock cycle, with every two subbands coefficients alternately. The total time for computing J levels of decomposition for an N×N image is approximately 2N2(1-4-J)/3 clock cycles. In comparison with the other devices reported in previous literature, the design has many advantages including lower hardware complexity and area and power efficiency. The design is also fast, regular and simple, as well as well suited for VLSI implementation.

Published in:

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on  (Volume:3 )

Date of Conference:

18-21 Oct. 2004