High performance synchronous DRAMs controller in H.264 HDTV decoder

This paper proposes a high efficiency memory controller for an H.264 HDTV decoder with synchronous DRAMs. As H.264 adopts tree structured (supports small block size) motion compensation, the bandwidth requirement of an H.264 HDTV decoder is higher than previous video processing algorithms. This requires to be optimized. Based on H.264 decoding data access behavior analysis, an SDRAM controller with new memory mapping method has been designed to reduce the overhead cycles of page-activation. Experiment results indicate that the new controller has improved by one-third the performance of the bus cycles. In addition, the architecture of the controller has also given low power consumption and less complexity in the VLSI design.