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Design of high speed arithmetic encoder [image coding applications]

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4 Author(s)
Mei Kuizhi ; Inst. of Artificial Intelligence & Robotics, Xi''an Jiaotong Univ., China ; Zhang Nanning ; Yao Ji ; Liu Yuehu

Focusing on the problem of path waiting or path circulation that existed in updating of the context table and the renorme and byteout procedure in the realization of the conventional arithmetic encoder in JPEG2000, a 3-step pipeline architecture is used on an FPGA to get high speed encoding. A method of updating the CX table is proposed, and a circuit with short delay is also implemented to detect the left zeros of the A-register. Multiplexers are adopted to accelerate the random left shift operation, and parallel processing based on data dependency is used to optimize the RTL code to shorten the main critical path. Finally, the updating of the logic of the context table is fully discussed. Experimental result show the encoder can work up to 107 MHz on Altera's EP1S25B672C7 and the critical path is 4.6 ns when synthesized in synopsys DC by the TSMC 0.25 μm library.

Published in:

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on  (Volume:3 )

Date of Conference:

18-21 Oct. 2004